These teachings relate generally to closed loop control systems and, more specifically, relate to frequency control loops such as automatic frequency control (AFC) circuits used in communications and other types of systems.
Coherent wireless communication receivers typically utilize an AFC or a FLL (frequency-locked loop) circuit to synchronize the frequency of a receiver to that of a transmitter.
The task of the AFC circuit is twofold. First, the AFC circuit must provide an initial frequency acquisition mode of operation, where large initial differences or errors between the transmitter frequency and the receiver frequency are reduced in value. Second, the AFC circuit must provide a frequency tracking or maintenance mode of operation, where the AFC circuit continuously attempts to drive the frequency error between the receiver and transmitter to zero in order to provide robust communications. AFC circuits are used in many wireless technologies including narrowband and wideband Code Division Multiple Access (CDMA) and Time Division Multiple Access (TDMA) systems. Examples of these systems include IS-95, IS-2000 (WCDMA) and GSM. In current standards a WCDMA system operates with a 5 MHz bandwidth, while a narrowband CDMA system operates with a 200 kHz bandwidth. AFC circuits are also used in television receivers, cable modems and a number of other types of systems wherein it is required to synchronize the operating frequency of a receiver to a received signal.
A conventional Digital AFC (DAFC) loop 1 is shown in FIG. 1. Reference can also be made to Fuyun Ling, xe2x80x9cConvergence and Output of Digital Frequency-Locked Loop for Wireless Communications,xe2x80x9d IEEE Trans. On Comm., May 1996. The DAFC loop 1 includes a mixer 2 that mixes a reference frequency output from a voltage controlled oscillator (VCO) 3 with that of an incoming received signal. The DAFC loop 1 further includes an analog to digital A/D converter 4, a frequency detector 5, a loop filter 6, an integrator 7, and a digital to analog converter (DAC) 8 that generates a frequency control voltage for the VCO 3. During operation the AFC loop 1 attempts to maintain, at the output of the integrator 7, a voltage that is proportional to the frequency offset that is present on the received signal. The A/D converter 4 samples and converts an analog signal output from the mixer 2 to a digital signal. The digital signal samples are sent to the frequency detector 5 which computes a difference, more precisely the 1st derivative, between successive samples. The output of the frequency detector 5 is analogous to the loop error signal. In the steady-state the output of the frequency detector 5 is (ideally) zero. Following the frequency detector 5 is the loop filter 6 that filters the error signal prior to the input of the integrator 7. In a multi-finger (multi-demodulator) rake receiver embodiment the frequency error outputs of those fingers having acceptable signal quality, as determined elsewhere in the receiver, are added in at summing junction 9. The composite signal is then input to the integrator circuit 7. At the output of the integrator 7 is the DAC 8, which converts the digital signal output from the integrator 7 to an analog signal or voltage. The DAC 8 then drives the VCO 3 with an analog voltage having a value that is proportional to the output frequency, thereby closing the DAFC control loop.
U.S. Pat. No.: 5,812,615, xe2x80x9cApparatus and method for maximizing frequency offset tracking performance in a digital receiverxe2x80x9d, Baum et al., discloses in FIG. 5 the use of sign determination circuits prior to a filter of an AFC unit used with a phase locked loop (PLL). An AFC unit includes a subtracter operating as a mixer, and the sign detectors detect phase errors that are mapped to one of +1, 0, xe2x88x921 values. The mapping process removes the amplitude information from a differential phase error and from a coherent phase error signal, while preserving the sign.
A problem that exists in the prior art results from the fact that conventional AFC circuits are typically optimized for use with a limited range of input signal levels, and compromises are thus made for signal levels outside of that range. These compromises tend to lead to a loss in performance.
A further problem relates to the fact in at least one design the frequency detector 5 is implemented using an arctan function (see Heinrich Meyr, Marc Moeneclaey, Stefan A. Fechtel, xe2x80x9cDigital Communication Receivers-Synchronization, Channel Estimation, and Signal Processing,xe2x80x9d John Wiley and Sons, Inc. 1998, pp. 478-481). While this approach generates a loop error signal that is substantially insensitive to signal level, this approach would not allow the loop to operate optimally in a rake receiver that uses Maximal Ratio Combining (MRC) of the frequency errors from different fingers.
A still further problem that is inherent in the prior art approach is in the combining of the frequency detector output and signal filtering, as scaling, normalization or limiting of the signal is required. In the prior art a normalization by the number of active fingers and limiting of the signal amplitude is typically required.
The foregoing and other problems are overcome, and other advantages are realized, in accordance with the presently preferred embodiments of these teachings.
This invention provides an automatic frequency control loop circuit that includes a mixer for mixing a local oscillator signal with a received signal to generate a result signal; a frequency detector coupled to the result signal and outputting a loop error signal; a combiner circuit for combining error signals output from a plurality of fingers of a rake receiver with the loop error signal output from the frequency detector to generate a combined loop error signal; a sign detector having an input coupled to an output of the combiner circuit for outputting a sign detector output signal for indicating a sign of the combined loop error signal; control circuitry for controlling a frequency of the local oscillator signal in accordance with the sign detector output signal and a loop filter partitioned into a first loop filter coupled between the output of the frequency detector and an input to the sign detector, and a second loop filter coupled between an output of the sign detector and an input to the control circuitry. In one embodiment the first loop filter is coupled between the output of the frequency detector and an input to the combiner circuit, while in another embodiment the first loop filter is coupled between the output of the combiner circuit and the input to the sign detector. The loop bandwidth is controlled with the loop filter, and the total required amount of loop filtering is split between the first loop filter and the second loop filter. In the preferred embodiment the combiner circuit is implemented as a Maximal Ratio Combining (MRC) circuit.